My name is Licheng Guo. I received my Ph.D. degree in 2022, my M.S. degree in 2021, both in Computer Science from UCLA. Prior to that I received my B.S. degree in Electronic Engineering from Zhejiang University in 2018.
My research focuses on co-optimizing HLS compilers (from C++ to RTL) and backend implementation tools (from RTL to bitstream) to improve the performance of domain-specific accelerators. I am the first author of two Best Papers in FPGA'21 and FPGA'22, based on which I co-founded RapidStream Design Automation after my graudation from UCLA.
I love travelling and aspire to explore every country of this amazing world :)